;buildInfoPackage: chisel3, version: 3.4.3, scalaVersion: 2.12.12, sbtVersion: 1.3.10
circuit top : 
  module Count_Clk : 
    input clock : Clock
    input reset : Reset
    output io : {Data_in : UInt<1>, count_clk_in : UInt<8>, count_clk_delay : UInt<8>, count_clk_enable : UInt<8>, count_clk_out : UInt<8>, flip Data : UInt<210>, flip stateReg : UInt<3>}
    
    reg count_clk_in : UInt<8>, clock with : (reset => (reset, UInt<8>("h00"))) @[PUF_Core.scala 132:36]
    reg count_clk_delay : UInt<8>, clock with : (reset => (reset, UInt<8>("h00"))) @[PUF_Core.scala 133:36]
    reg count_clk_enable : UInt<8>, clock with : (reset => (reset, UInt<8>("h00"))) @[PUF_Core.scala 134:36]
    reg count_clk_out : UInt<8>, clock with : (reset => (reset, UInt<8>("h00"))) @[PUF_Core.scala 135:36]
    wire the_data_in : UInt<1> @[PUF_Core.scala 136:33]
    node _the_data_in_T = dshr(io.Data, count_clk_in) @[PUF_Core.scala 138:35]
    node _the_data_in_T_1 = bits(_the_data_in_T, 0, 0) @[PUF_Core.scala 138:52]
    the_data_in <= _the_data_in_T_1 @[PUF_Core.scala 138:21]
    node _T = eq(io.stateReg, UInt<3>("h01")) @[PUF_Core.scala 140:23]
    when _T : @[PUF_Core.scala 140:36]
      node _count_clk_in_T = add(count_clk_in, UInt<1>("h01")) @[PUF_Core.scala 141:42]
      node _count_clk_in_T_1 = tail(_count_clk_in_T, 1) @[PUF_Core.scala 141:42]
      count_clk_in <= _count_clk_in_T_1 @[PUF_Core.scala 141:25]
      skip @[PUF_Core.scala 140:36]
    else : @[PUF_Core.scala 142:16]
      count_clk_in <= UInt<1>("h00") @[PUF_Core.scala 143:25]
      skip @[PUF_Core.scala 142:16]
    node _T_1 = eq(io.stateReg, UInt<3>("h02")) @[PUF_Core.scala 146:23]
    when _T_1 : @[PUF_Core.scala 146:36]
      node _count_clk_delay_T = add(count_clk_delay, UInt<1>("h01")) @[PUF_Core.scala 147:45]
      node _count_clk_delay_T_1 = tail(_count_clk_delay_T, 1) @[PUF_Core.scala 147:45]
      count_clk_delay <= _count_clk_delay_T_1 @[PUF_Core.scala 147:25]
      skip @[PUF_Core.scala 146:36]
    else : @[PUF_Core.scala 149:15]
      count_clk_delay <= UInt<1>("h00") @[PUF_Core.scala 150:25]
      skip @[PUF_Core.scala 149:15]
    node _T_2 = eq(io.stateReg, UInt<3>("h03")) @[PUF_Core.scala 153:23]
    when _T_2 : @[PUF_Core.scala 153:37]
      node _count_clk_enable_T = add(count_clk_enable, UInt<1>("h01")) @[PUF_Core.scala 154:50]
      node _count_clk_enable_T_1 = tail(_count_clk_enable_T, 1) @[PUF_Core.scala 154:50]
      count_clk_enable <= _count_clk_enable_T_1 @[PUF_Core.scala 154:29]
      skip @[PUF_Core.scala 153:37]
    else : @[PUF_Core.scala 156:15]
      count_clk_enable <= UInt<1>("h00") @[PUF_Core.scala 157:29]
      skip @[PUF_Core.scala 156:15]
    node _T_3 = eq(io.stateReg, UInt<3>("h04")) @[PUF_Core.scala 160:23]
    when _T_3 : @[PUF_Core.scala 160:37]
      node _count_clk_out_T = add(count_clk_out, UInt<1>("h01")) @[PUF_Core.scala 161:43]
      node _count_clk_out_T_1 = tail(_count_clk_out_T, 1) @[PUF_Core.scala 161:43]
      count_clk_out <= _count_clk_out_T_1 @[PUF_Core.scala 161:25]
      skip @[PUF_Core.scala 160:37]
    else : @[PUF_Core.scala 163:15]
      count_clk_out <= UInt<1>("h00") @[PUF_Core.scala 164:25]
      skip @[PUF_Core.scala 163:15]
    io.Data_in <= the_data_in @[PUF_Core.scala 167:25]
    io.count_clk_in <= count_clk_in @[PUF_Core.scala 168:25]
    io.count_clk_delay <= count_clk_delay @[PUF_Core.scala 169:25]
    io.count_clk_enable <= count_clk_enable @[PUF_Core.scala 170:25]
    io.count_clk_out <= count_clk_out @[PUF_Core.scala 171:25]
    
  module PUF_Core : 
    input clock : Clock
    input reset : Reset
    output io : {out : {Data_in : UInt<1>, Ena_in : UInt<1>, Clk_in : UInt<1>, Ena_out : UInt<1>, Clk_out : UInt<1>}, in : {flip Start : UInt<1>, flip Data : UInt<210>}, clk : {flip Clk : Clock}}
    
    wire the_ena_in : UInt<1> @[PUF_Core.scala 17:33]
    reg the_ena_out : UInt<1>, clock @[PUF_Core.scala 18:32]
    wire the_clk_in : UInt<1> @[PUF_Core.scala 19:33]
    wire the_clk_out : UInt<1> @[PUF_Core.scala 20:33]
    wire the_data_in : UInt<1> @[PUF_Core.scala 21:33]
    io.out.Data_in <= the_data_in @[PUF_Core.scala 23:25]
    io.out.Ena_in <= the_ena_in @[PUF_Core.scala 24:25]
    reg io_out_Ena_out_REG : UInt<1>, clock @[PUF_Core.scala 25:36]
    io_out_Ena_out_REG <= the_ena_out @[PUF_Core.scala 25:36]
    io.out.Ena_out <= io_out_Ena_out_REG @[PUF_Core.scala 25:25]
    io.out.Clk_in <= the_clk_in @[PUF_Core.scala 26:25]
    io.out.Clk_out <= the_clk_out @[PUF_Core.scala 27:25]
    wire count_clk_in : UInt<8>
    count_clk_in <= UInt<8>("h00")
    wire count_clk_delay : UInt<8>
    count_clk_delay <= UInt<8>("h00")
    wire count_clk_enable : UInt<8>
    count_clk_enable <= UInt<8>("h00")
    wire count_clk_out : UInt<8>
    count_clk_out <= UInt<8>("h00")
    wire trigger_input : UInt<1> @[PUF_Core.scala 34:33]
    wire trigger_delay : UInt<1> @[PUF_Core.scala 35:33]
    wire trigger_enable : UInt<1> @[PUF_Core.scala 36:33]
    wire trigger_output : UInt<1> @[PUF_Core.scala 37:33]
    wire trigger_idle : UInt<1> @[PUF_Core.scala 38:33]
    trigger_input <= io.in.Start @[PUF_Core.scala 40:25]
    node _trigger_delay_T = eq(count_clk_in, UInt<8>("h0d2")) @[PUF_Core.scala 41:44]
    trigger_delay <= _trigger_delay_T @[PUF_Core.scala 41:25]
    node _trigger_enable_T = eq(count_clk_delay, UInt<3>("h04")) @[PUF_Core.scala 42:47]
    trigger_enable <= _trigger_enable_T @[PUF_Core.scala 42:25]
    node _trigger_output_T = eq(count_clk_enable, UInt<2>("h02")) @[PUF_Core.scala 43:48]
    trigger_output <= _trigger_output_T @[PUF_Core.scala 43:25]
    node _trigger_idle_T = sub(UInt<8>("h080"), UInt<2>("h02")) @[PUF_Core.scala 44:61]
    node _trigger_idle_T_1 = tail(_trigger_idle_T, 1) @[PUF_Core.scala 44:61]
    node _trigger_idle_T_2 = eq(count_clk_out, _trigger_idle_T_1) @[PUF_Core.scala 44:45]
    trigger_idle <= _trigger_idle_T_2 @[PUF_Core.scala 44:25]
    reg stateReg : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[PUF_Core.scala 48:32]
    inst M_Count_Clk of Count_Clk @[PUF_Core.scala 50:39]
    M_Count_Clk.clock <= clock
    M_Count_Clk.reset <= reset
    M_Count_Clk.clock <= io.clk.Clk @[PUF_Core.scala 51:29]
    M_Count_Clk.io.Data <= io.in.Data @[PUF_Core.scala 52:29]
    M_Count_Clk.io.stateReg <= stateReg @[PUF_Core.scala 53:29]
    count_clk_in <= M_Count_Clk.io.count_clk_in @[PUF_Core.scala 54:29]
    count_clk_delay <= M_Count_Clk.io.count_clk_delay @[PUF_Core.scala 55:29]
    count_clk_enable <= M_Count_Clk.io.count_clk_enable @[PUF_Core.scala 56:29]
    count_clk_out <= M_Count_Clk.io.count_clk_out @[PUF_Core.scala 57:29]
    the_data_in <= M_Count_Clk.io.Data_in @[PUF_Core.scala 58:29]
    node _T = eq(stateReg, UInt<3>("h01")) @[PUF_Core.scala 60:20]
    when _T : @[PUF_Core.scala 60:33]
      the_ena_in <= UInt<1>("h00") @[PUF_Core.scala 61:25]
      the_ena_out <= UInt<1>("h00") @[PUF_Core.scala 62:25]
      the_clk_in <= UInt<1>("h01") @[PUF_Core.scala 63:25]
      the_clk_out <= UInt<1>("h00") @[PUF_Core.scala 64:25]
      skip @[PUF_Core.scala 60:33]
    else : @[PUF_Core.scala 66:38]
      node _T_1 = eq(stateReg, UInt<3>("h02")) @[PUF_Core.scala 66:25]
      when _T_1 : @[PUF_Core.scala 66:38]
        the_ena_in <= UInt<1>("h01") @[PUF_Core.scala 67:25]
        the_ena_out <= UInt<1>("h00") @[PUF_Core.scala 68:25]
        the_clk_in <= UInt<1>("h00") @[PUF_Core.scala 69:25]
        the_clk_out <= UInt<1>("h00") @[PUF_Core.scala 70:25]
        skip @[PUF_Core.scala 66:38]
      else : @[PUF_Core.scala 72:39]
        node _T_2 = eq(stateReg, UInt<3>("h03")) @[PUF_Core.scala 72:25]
        when _T_2 : @[PUF_Core.scala 72:39]
          the_ena_in <= UInt<1>("h01") @[PUF_Core.scala 73:25]
          the_ena_out <= UInt<1>("h01") @[PUF_Core.scala 74:25]
          the_clk_in <= UInt<1>("h00") @[PUF_Core.scala 75:25]
          the_clk_out <= UInt<1>("h01") @[PUF_Core.scala 76:25]
          skip @[PUF_Core.scala 72:39]
        else : @[PUF_Core.scala 78:39]
          node _T_3 = eq(stateReg, UInt<3>("h04")) @[PUF_Core.scala 78:25]
          when _T_3 : @[PUF_Core.scala 78:39]
            the_ena_in <= UInt<1>("h00") @[PUF_Core.scala 79:25]
            the_ena_out <= UInt<1>("h01") @[PUF_Core.scala 80:25]
            the_clk_in <= UInt<1>("h01") @[PUF_Core.scala 81:25]
            the_clk_out <= UInt<1>("h01") @[PUF_Core.scala 82:25]
            skip @[PUF_Core.scala 78:39]
          else : @[PUF_Core.scala 84:15]
            the_ena_in <= UInt<1>("h00") @[PUF_Core.scala 85:25]
            the_ena_out <= UInt<1>("h00") @[PUF_Core.scala 86:25]
            the_clk_in <= UInt<1>("h00") @[PUF_Core.scala 87:25]
            the_clk_out <= UInt<1>("h00") @[PUF_Core.scala 88:25]
            skip @[PUF_Core.scala 84:15]
    node _T_4 = eq(stateReg, UInt<3>("h01")) @[PUF_Core.scala 92:20]
    when _T_4 : @[PUF_Core.scala 92:33]
      when trigger_delay : @[PUF_Core.scala 93:31]
        stateReg <= UInt<3>("h02") @[PUF_Core.scala 94:25]
        skip @[PUF_Core.scala 93:31]
      skip @[PUF_Core.scala 92:33]
    else : @[PUF_Core.scala 97:38]
      node _T_5 = eq(stateReg, UInt<3>("h02")) @[PUF_Core.scala 97:25]
      when _T_5 : @[PUF_Core.scala 97:38]
        when trigger_enable : @[PUF_Core.scala 98:31]
          stateReg <= UInt<3>("h03") @[PUF_Core.scala 99:25]
          skip @[PUF_Core.scala 98:31]
        skip @[PUF_Core.scala 97:38]
      else : @[PUF_Core.scala 102:38]
        node _T_6 = eq(stateReg, UInt<3>("h03")) @[PUF_Core.scala 102:25]
        when _T_6 : @[PUF_Core.scala 102:38]
          when trigger_output : @[PUF_Core.scala 103:32]
            stateReg <= UInt<3>("h04") @[PUF_Core.scala 104:25]
            skip @[PUF_Core.scala 103:32]
          skip @[PUF_Core.scala 102:38]
        else : @[PUF_Core.scala 107:38]
          node _T_7 = eq(stateReg, UInt<3>("h04")) @[PUF_Core.scala 107:25]
          when _T_7 : @[PUF_Core.scala 107:38]
            when trigger_idle : @[PUF_Core.scala 108:30]
              stateReg <= UInt<3>("h00") @[PUF_Core.scala 109:25]
              skip @[PUF_Core.scala 108:30]
            skip @[PUF_Core.scala 107:38]
          else : @[PUF_Core.scala 112:16]
            when trigger_input : @[PUF_Core.scala 113:31]
              stateReg <= UInt<3>("h01") @[PUF_Core.scala 114:25]
              skip @[PUF_Core.scala 113:31]
            skip @[PUF_Core.scala 112:16]
    
  module Clk_Divider : 
    input clock : Clock
    input reset : Reset
    output io : {clk_out : Clock}
    
    reg the_clk : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Clk_Divider.scala 14:28]
    node _the_clk_T = not(the_clk) @[Clk_Divider.scala 15:21]
    the_clk <= _the_clk_T @[Clk_Divider.scala 15:17]
    node _io_clk_out_T = asClock(the_clk) @[Clk_Divider.scala 17:29]
    io.clk_out <= _io_clk_out_T @[Clk_Divider.scala 17:17]
    
  module core : 
    input clock : Clock
    input reset : Reset
    output io : {out : {Data_in : UInt<1>, Ena_in : UInt<1>, Clk_in : UInt<1>, Ena_out : UInt<1>, Clk_out : UInt<1>, Clk : UInt<1>}}
    
    inst M_PUF_Core of PUF_Core @[PUF_Top.scala 34:35]
    M_PUF_Core.clock <= clock
    M_PUF_Core.reset <= reset
    inst the_clock_M_Clk_Divider of Clk_Divider @[Clk_Divider.scala 23:35]
    the_clock_M_Clk_Divider.clock <= clock
    the_clock_M_Clk_Divider.reset <= reset
    wire the_clock_reverse : Clock @[PUF_Top.scala 37:37]
    node _the_clock_reverse_T = asUInt(the_clock_M_Clk_Divider.io.clk_out) @[PUF_Top.scala 38:47]
    node _the_clock_reverse_T_1 = bits(_the_clock_reverse_T, 0, 0) @[PUF_Top.scala 38:47]
    node _the_clock_reverse_T_2 = mux(_the_clock_reverse_T_1, UInt<1>("h00"), UInt<1>("h01")) @[PUF_Top.scala 38:36]
    node _the_clock_reverse_T_3 = asClock(_the_clock_reverse_T_2) @[PUF_Top.scala 38:72]
    the_clock_reverse <= _the_clock_reverse_T_3 @[PUF_Top.scala 38:29]
    M_PUF_Core.io.clk.Clk <= the_clock_reverse @[PUF_Top.scala 40:29]
    M_PUF_Core.io.in.Start <= UInt<1>("h01") @[PUF_Top.scala 41:29]
    M_PUF_Core.io.in.Data <= UInt<224>("h0aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa") @[PUF_Top.scala 42:29]
    reg the_ena_in : UInt<1>, clock @[PUF_Top.scala 50:40]
    the_ena_in <= M_PUF_Core.io.out.Ena_in @[PUF_Top.scala 50:40]
    node _the_clk_in_T = asUInt(the_clock_M_Clk_Divider.io.clk_out) @[PUF_Top.scala 51:79]
    node _the_clk_in_T_1 = bits(_the_clk_in_T, 0, 0) @[PUF_Top.scala 51:86]
    node _the_clk_in_T_2 = and(M_PUF_Core.io.out.Clk_in, _the_clk_in_T_1) @[PUF_Top.scala 51:66]
    reg the_clk_in : UInt<1>, clock @[PUF_Top.scala 51:40]
    the_clk_in <= _the_clk_in_T_2 @[PUF_Top.scala 51:40]
    reg io_out_Data_in_REG : UInt, clock @[PUF_Top.scala 54:40]
    io_out_Data_in_REG <= M_PUF_Core.io.out.Data_in @[PUF_Top.scala 54:40]
    io.out.Data_in <= io_out_Data_in_REG @[PUF_Top.scala 54:29]
    io.out.Ena_in <= the_ena_in @[PUF_Top.scala 55:29]
    reg io_out_Ena_out_REG : UInt<1>, clock @[PUF_Top.scala 56:40]
    io_out_Ena_out_REG <= M_PUF_Core.io.out.Ena_out @[PUF_Top.scala 56:40]
    io.out.Ena_out <= io_out_Ena_out_REG @[PUF_Top.scala 56:29]
    io.out.Clk_in <= the_clk_in @[PUF_Top.scala 57:29]
    node _io_out_Clk_out_T = asUInt(the_clock_reverse) @[PUF_Top.scala 58:88]
    node _io_out_Clk_out_T_1 = bits(_io_out_Clk_out_T, 0, 0) @[PUF_Top.scala 58:95]
    node _io_out_Clk_out_T_2 = and(M_PUF_Core.io.out.Clk_out, _io_out_Clk_out_T_1) @[PUF_Top.scala 58:67]
    reg io_out_Clk_out_REG : UInt<1>, clock @[PUF_Top.scala 58:40]
    io_out_Clk_out_REG <= _io_out_Clk_out_T_2 @[PUF_Top.scala 58:40]
    io.out.Clk_out <= io_out_Clk_out_REG @[PUF_Top.scala 58:29]
    reg io_out_Clk_REG : UInt<1>, clock @[PUF_Top.scala 59:64]
    io_out_Clk_REG <= the_ena_in @[PUF_Top.scala 59:64]
    reg io_out_Clk_REG_1 : UInt<1>, clock @[PUF_Top.scala 59:56]
    io_out_Clk_REG_1 <= io_out_Clk_REG @[PUF_Top.scala 59:56]
    reg io_out_Clk_REG_2 : UInt<1>, clock @[PUF_Top.scala 59:48]
    io_out_Clk_REG_2 <= io_out_Clk_REG_1 @[PUF_Top.scala 59:48]
    reg io_out_Clk_REG_3 : UInt<1>, clock @[PUF_Top.scala 59:40]
    io_out_Clk_REG_3 <= io_out_Clk_REG_2 @[PUF_Top.scala 59:40]
    io.out.Clk <= io_out_Clk_REG_3 @[PUF_Top.scala 59:29]
    
  extmodule clk_divider : 
    input clk : Clock
    input rst_p : UInt<1>
    output clk_div : Clock
    
    defname = clk_divider
    parameter NUM_DIV = 100
    parameter CNT_LEN = 8
    
  module top : 
    input clock : Clock
    input reset : UInt<1>
    output io : {out : {Data_in : UInt<1>, Ena_in : UInt<1>, Clk_in : UInt<1>, Ena_out : UInt<1>, Clk_out : UInt<1>, Clk : UInt<1>}}
    
    inst M_Core of core @[PUF_Top.scala 16:35]
    M_Core.clock <= clock
    M_Core.reset <= reset
    wire the_clock : Clock @[PUF_Top.scala 18:33]
    inst M_Clk_Divider of clk_divider @[PUF_Top.scala 19:35]
    M_Clk_Divider.clk_div is invalid
    M_Clk_Divider.rst_p is invalid
    M_Clk_Divider.clk is invalid
    M_Clk_Divider.clk <= clock @[PUF_Top.scala 20:29]
    node _M_Clk_Divider_io_rst_p_T = bits(reset, 0, 0) @[PUF_Top.scala 21:39]
    M_Clk_Divider.rst_p <= _M_Clk_Divider_io_rst_p_T @[PUF_Top.scala 21:29]
    the_clock <= M_Clk_Divider.clk_div @[PUF_Top.scala 22:29]
    M_Core.clock <= the_clock @[PUF_Top.scala 24:21]
    io.out.Clk <= M_Core.io.out.Clk @[PUF_Top.scala 25:21]
    io.out.Clk_out <= M_Core.io.out.Clk_out @[PUF_Top.scala 25:21]
    io.out.Ena_out <= M_Core.io.out.Ena_out @[PUF_Top.scala 25:21]
    io.out.Clk_in <= M_Core.io.out.Clk_in @[PUF_Top.scala 25:21]
    io.out.Ena_in <= M_Core.io.out.Ena_in @[PUF_Top.scala 25:21]
    io.out.Data_in <= M_Core.io.out.Data_in @[PUF_Top.scala 25:21]
    
